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clocks.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_CLOCKS_H
9#define _HARDWARE_STRUCTS_CLOCKS_H
10
16#include "hardware/regs/clocks.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
44
98
100typedef struct {
101 _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
102 // Clock control, can be changed on-the-fly (except for auxsrc)
103 // 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by...
104 // 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the...
105 // 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors
106 // 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly
107 // 0x00000400 [10] KILL (0) Asynchronously kills the clock generator
108 // 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching
109 io_rw_32 ctrl;
110
111 _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
112 // Clock divisor, can be changed on-the-fly
113 // 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16
114 // 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor
115 io_rw_32 div;
116
117 _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
118 // Indicates which SRC is currently selected by the glitchless mux (one-hot)
119 // 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the...
120 io_ro_32 selected;
121} clock_hw_t;
123
124typedef struct {
125 _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
126 // 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it...
127 // 0x00001000 [12] FRCE (0) Force a resus, for test purposes only
128 // 0x00000100 [8] ENABLE (0) Enable resus
129 // 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles +
130 io_rw_32 ctrl;
131
132 _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
133 // 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send...
134 io_ro_32 status;
136
137typedef struct {
138 _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
139 // Reference clock frequency in kHz
140 // 0x000fffff [19:0] FC0_REF_KHZ (0x00000)
141 io_rw_32 ref_khz;
142
143 _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
144 // Minimum pass frequency in kHz
145 // 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000)
146 io_rw_32 min_khz;
147
148 _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
149 // Maximum pass frequency in kHz
150 // 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff)
151 io_rw_32 max_khz;
152
153 _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
154 // Delays the start of frequency counting to allow the mux to settle +
155 // 0x00000007 [2:0] FC0_DELAY (0x1)
156 io_rw_32 delay;
157
158 _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
159 // The test interval is 0
160 // 0x0000000f [3:0] FC0_INTERVAL (0x8)
161 io_rw_32 interval;
162
163 _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
164 // Clock sent to frequency counter, set to 0 when not required +
165 // 0x000000ff [7:0] FC0_SRC (0x00)
166 io_rw_32 src;
167
168 _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
169 // Frequency counter status
170 // 0x10000000 [28] DIED (0) Test clock stopped during test
171 // 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1
172 // 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1
173 // 0x00010000 [16] FAIL (0) Test failed
174 // 0x00001000 [12] WAITING (0) Waiting for test clock to start
175 // 0x00000100 [8] RUNNING (0) Test running
176 // 0x00000010 [4] DONE (0) Test complete
177 // 0x00000001 [0] PASS (0) Test passed
178 io_ro_32 status;
179
180 _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
181 // Result of frequency measurement, only valid when status_done=1
182 // 0x3fffffe0 [29:5] KHZ (0x0000000)
183 // 0x0000001f [4:0] FRAC (0x00)
184 io_ro_32 result;
185} fc_hw_t;
186
187typedef struct {
188 clock_hw_t clk[10];
189
190 clock_resus_hw_t resus;
191
192 fc_hw_t fc0;
193
194 union {
195 struct {
196 _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
197 // enable clock in wake mode
198 // 0x80000000 [31] CLK_SYS_SRAM3 (1)
199 // 0x40000000 [30] CLK_SYS_SRAM2 (1)
200 // 0x20000000 [29] CLK_SYS_SRAM1 (1)
201 // 0x10000000 [28] CLK_SYS_SRAM0 (1)
202 // 0x08000000 [27] CLK_SYS_SPI1 (1)
203 // 0x04000000 [26] CLK_PERI_SPI1 (1)
204 // 0x02000000 [25] CLK_SYS_SPI0 (1)
205 // 0x01000000 [24] CLK_PERI_SPI0 (1)
206 // 0x00800000 [23] CLK_SYS_SIOB (1)
207 // 0x00400000 [22] CLK_SYS_RTC (1)
208 // 0x00200000 [21] CLK_RTC_RTC (1)
209 // 0x00100000 [20] CLK_SYS_ROSC (1)
210 // 0x00080000 [19] CLK_SYS_ROM (1)
211 // 0x00040000 [18] CLK_SYS_RESETS (1)
212 // 0x00020000 [17] CLK_SYS_PWM (1)
213 // 0x00010000 [16] CLK_SYS_POWER (1)
214 // 0x00008000 [15] CLK_SYS_PLL_USB (1)
215 // 0x00004000 [14] CLK_SYS_PLL_SYS (1)
216 // 0x00002000 [13] CLK_SYS_PIO1 (1)
217 // 0x00001000 [12] CLK_SYS_PIO0 (1)
218 // 0x00000800 [11] CLK_SYS_PADS (1)
219 // 0x00000400 [10] CLK_SYS_LDO_POR (1)
220 // 0x00000200 [9] CLK_SYS_JTAG (1)
221 // 0x00000100 [8] CLK_SYS_IO (1)
222 // 0x00000080 [7] CLK_SYS_I2C1 (1)
223 // 0x00000040 [6] CLK_SYS_I2C0 (1)
224 // 0x00000020 [5] CLK_SYS_DMA (1)
225 // 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
226 // 0x00000008 [3] CLK_SYS_BUSCTRL (1)
227 // 0x00000004 [2] CLK_SYS_ADC0 (1)
228 // 0x00000002 [1] CLK_ADC_ADC0 (1)
229 // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
230 io_rw_32 wake_en0;
231
232 _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
233 // enable clock in wake mode
234 // 0x00004000 [14] CLK_SYS_XOSC (1)
235 // 0x00002000 [13] CLK_SYS_XIP (1)
236 // 0x00001000 [12] CLK_SYS_WATCHDOG (1)
237 // 0x00000800 [11] CLK_USB_USBCTRL (1)
238 // 0x00000400 [10] CLK_SYS_USBCTRL (1)
239 // 0x00000200 [9] CLK_SYS_UART1 (1)
240 // 0x00000100 [8] CLK_PERI_UART1 (1)
241 // 0x00000080 [7] CLK_SYS_UART0 (1)
242 // 0x00000040 [6] CLK_PERI_UART0 (1)
243 // 0x00000020 [5] CLK_SYS_TIMER (1)
244 // 0x00000010 [4] CLK_SYS_TBMAN (1)
245 // 0x00000008 [3] CLK_SYS_SYSINFO (1)
246 // 0x00000004 [2] CLK_SYS_SYSCFG (1)
247 // 0x00000002 [1] CLK_SYS_SRAM5 (1)
248 // 0x00000001 [0] CLK_SYS_SRAM4 (1)
249 io_rw_32 wake_en1;
250 };
251 // (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes)
252 _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
253 // enable clock in wake mode
254 // 0x80000000 [31] CLK_SYS_SRAM3 (1)
255 // 0x40000000 [30] CLK_SYS_SRAM2 (1)
256 // 0x20000000 [29] CLK_SYS_SRAM1 (1)
257 // 0x10000000 [28] CLK_SYS_SRAM0 (1)
258 // 0x08000000 [27] CLK_SYS_SPI1 (1)
259 // 0x04000000 [26] CLK_PERI_SPI1 (1)
260 // 0x02000000 [25] CLK_SYS_SPI0 (1)
261 // 0x01000000 [24] CLK_PERI_SPI0 (1)
262 // 0x00800000 [23] CLK_SYS_SIO (1)
263 // 0x00400000 [22] CLK_SYS_RTC (1)
264 // 0x00200000 [21] CLK_RTC_RTC (1)
265 // 0x00100000 [20] CLK_SYS_ROSC (1)
266 // 0x00080000 [19] CLK_SYS_ROM (1)
267 // 0x00040000 [18] CLK_SYS_RESETS (1)
268 // 0x00020000 [17] CLK_SYS_PWM (1)
269 // 0x00010000 [16] CLK_SYS_PSM (1)
270 // 0x00008000 [15] CLK_SYS_PLL_USB (1)
271 // 0x00004000 [14] CLK_SYS_PLL_SYS (1)
272 // 0x00002000 [13] CLK_SYS_PIO1 (1)
273 // 0x00001000 [12] CLK_SYS_PIO0 (1)
274 // 0x00000800 [11] CLK_SYS_PADS (1)
275 // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
276 // 0x00000200 [9] CLK_SYS_JTAG (1)
277 // 0x00000100 [8] CLK_SYS_IO (1)
278 // 0x00000080 [7] CLK_SYS_I2C1 (1)
279 // 0x00000040 [6] CLK_SYS_I2C0 (1)
280 // 0x00000020 [5] CLK_SYS_DMA (1)
281 // 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
282 // 0x00000008 [3] CLK_SYS_BUSCTRL (1)
283 // 0x00000004 [2] CLK_SYS_ADC (1)
284 // 0x00000002 [1] CLK_ADC_ADC (1)
285 // 0x00000001 [0] CLK_SYS_CLOCKS (1)
286 io_rw_32 wake_en[2];
287 };
288
289 union {
290 struct {
291 _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
292 // enable clock in sleep mode
293 // 0x80000000 [31] CLK_SYS_SRAM3 (1)
294 // 0x40000000 [30] CLK_SYS_SRAM2 (1)
295 // 0x20000000 [29] CLK_SYS_SRAM1 (1)
296 // 0x10000000 [28] CLK_SYS_SRAM0 (1)
297 // 0x08000000 [27] CLK_SYS_SPI1 (1)
298 // 0x04000000 [26] CLK_PERI_SPI1 (1)
299 // 0x02000000 [25] CLK_SYS_SPI0 (1)
300 // 0x01000000 [24] CLK_PERI_SPI0 (1)
301 // 0x00800000 [23] CLK_SYS_SIOB (1)
302 // 0x00400000 [22] CLK_SYS_RTC (1)
303 // 0x00200000 [21] CLK_RTC_RTC (1)
304 // 0x00100000 [20] CLK_SYS_ROSC (1)
305 // 0x00080000 [19] CLK_SYS_ROM (1)
306 // 0x00040000 [18] CLK_SYS_RESETS (1)
307 // 0x00020000 [17] CLK_SYS_PWM (1)
308 // 0x00010000 [16] CLK_SYS_POWER (1)
309 // 0x00008000 [15] CLK_SYS_PLL_USB (1)
310 // 0x00004000 [14] CLK_SYS_PLL_SYS (1)
311 // 0x00002000 [13] CLK_SYS_PIO1 (1)
312 // 0x00001000 [12] CLK_SYS_PIO0 (1)
313 // 0x00000800 [11] CLK_SYS_PADS (1)
314 // 0x00000400 [10] CLK_SYS_LDO_POR (1)
315 // 0x00000200 [9] CLK_SYS_JTAG (1)
316 // 0x00000100 [8] CLK_SYS_IO (1)
317 // 0x00000080 [7] CLK_SYS_I2C1 (1)
318 // 0x00000040 [6] CLK_SYS_I2C0 (1)
319 // 0x00000020 [5] CLK_SYS_DMA (1)
320 // 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
321 // 0x00000008 [3] CLK_SYS_BUSCTRL (1)
322 // 0x00000004 [2] CLK_SYS_ADC0 (1)
323 // 0x00000002 [1] CLK_ADC_ADC0 (1)
324 // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
325 io_rw_32 sleep_en0;
326
327 _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
328 // enable clock in sleep mode
329 // 0x00004000 [14] CLK_SYS_XOSC (1)
330 // 0x00002000 [13] CLK_SYS_XIP (1)
331 // 0x00001000 [12] CLK_SYS_WATCHDOG (1)
332 // 0x00000800 [11] CLK_USB_USBCTRL (1)
333 // 0x00000400 [10] CLK_SYS_USBCTRL (1)
334 // 0x00000200 [9] CLK_SYS_UART1 (1)
335 // 0x00000100 [8] CLK_PERI_UART1 (1)
336 // 0x00000080 [7] CLK_SYS_UART0 (1)
337 // 0x00000040 [6] CLK_PERI_UART0 (1)
338 // 0x00000020 [5] CLK_SYS_TIMER (1)
339 // 0x00000010 [4] CLK_SYS_TBMAN (1)
340 // 0x00000008 [3] CLK_SYS_SYSINFO (1)
341 // 0x00000004 [2] CLK_SYS_SYSCFG (1)
342 // 0x00000002 [1] CLK_SYS_SRAM5 (1)
343 // 0x00000001 [0] CLK_SYS_SRAM4 (1)
344 io_rw_32 sleep_en1;
345 };
346 // (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes)
347 _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
348 // enable clock in sleep mode
349 // 0x80000000 [31] CLK_SYS_SRAM3 (1)
350 // 0x40000000 [30] CLK_SYS_SRAM2 (1)
351 // 0x20000000 [29] CLK_SYS_SRAM1 (1)
352 // 0x10000000 [28] CLK_SYS_SRAM0 (1)
353 // 0x08000000 [27] CLK_SYS_SPI1 (1)
354 // 0x04000000 [26] CLK_PERI_SPI1 (1)
355 // 0x02000000 [25] CLK_SYS_SPI0 (1)
356 // 0x01000000 [24] CLK_PERI_SPI0 (1)
357 // 0x00800000 [23] CLK_SYS_SIO (1)
358 // 0x00400000 [22] CLK_SYS_RTC (1)
359 // 0x00200000 [21] CLK_RTC_RTC (1)
360 // 0x00100000 [20] CLK_SYS_ROSC (1)
361 // 0x00080000 [19] CLK_SYS_ROM (1)
362 // 0x00040000 [18] CLK_SYS_RESETS (1)
363 // 0x00020000 [17] CLK_SYS_PWM (1)
364 // 0x00010000 [16] CLK_SYS_PSM (1)
365 // 0x00008000 [15] CLK_SYS_PLL_USB (1)
366 // 0x00004000 [14] CLK_SYS_PLL_SYS (1)
367 // 0x00002000 [13] CLK_SYS_PIO1 (1)
368 // 0x00001000 [12] CLK_SYS_PIO0 (1)
369 // 0x00000800 [11] CLK_SYS_PADS (1)
370 // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
371 // 0x00000200 [9] CLK_SYS_JTAG (1)
372 // 0x00000100 [8] CLK_SYS_IO (1)
373 // 0x00000080 [7] CLK_SYS_I2C1 (1)
374 // 0x00000040 [6] CLK_SYS_I2C0 (1)
375 // 0x00000020 [5] CLK_SYS_DMA (1)
376 // 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
377 // 0x00000008 [3] CLK_SYS_BUSCTRL (1)
378 // 0x00000004 [2] CLK_SYS_ADC (1)
379 // 0x00000002 [1] CLK_ADC_ADC (1)
380 // 0x00000001 [0] CLK_SYS_CLOCKS (1)
381 io_rw_32 sleep_en[2];
382 };
383
384 union {
385 struct {
386 _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
387 // indicates the state of the clock enable
388 // 0x80000000 [31] CLK_SYS_SRAM3 (0)
389 // 0x40000000 [30] CLK_SYS_SRAM2 (0)
390 // 0x20000000 [29] CLK_SYS_SRAM1 (0)
391 // 0x10000000 [28] CLK_SYS_SRAM0 (0)
392 // 0x08000000 [27] CLK_SYS_SPI1 (0)
393 // 0x04000000 [26] CLK_PERI_SPI1 (0)
394 // 0x02000000 [25] CLK_SYS_SPI0 (0)
395 // 0x01000000 [24] CLK_PERI_SPI0 (0)
396 // 0x00800000 [23] CLK_SYS_SIOB (0)
397 // 0x00400000 [22] CLK_SYS_RTC (0)
398 // 0x00200000 [21] CLK_RTC_RTC (0)
399 // 0x00100000 [20] CLK_SYS_ROSC (0)
400 // 0x00080000 [19] CLK_SYS_ROM (0)
401 // 0x00040000 [18] CLK_SYS_RESETS (0)
402 // 0x00020000 [17] CLK_SYS_PWM (0)
403 // 0x00010000 [16] CLK_SYS_POWER (0)
404 // 0x00008000 [15] CLK_SYS_PLL_USB (0)
405 // 0x00004000 [14] CLK_SYS_PLL_SYS (0)
406 // 0x00002000 [13] CLK_SYS_PIO1 (0)
407 // 0x00001000 [12] CLK_SYS_PIO0 (0)
408 // 0x00000800 [11] CLK_SYS_PADS (0)
409 // 0x00000400 [10] CLK_SYS_LDO_POR (0)
410 // 0x00000200 [9] CLK_SYS_JTAG (0)
411 // 0x00000100 [8] CLK_SYS_IO (0)
412 // 0x00000080 [7] CLK_SYS_I2C1 (0)
413 // 0x00000040 [6] CLK_SYS_I2C0 (0)
414 // 0x00000020 [5] CLK_SYS_DMA (0)
415 // 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
416 // 0x00000008 [3] CLK_SYS_BUSCTRL (0)
417 // 0x00000004 [2] CLK_SYS_ADC0 (0)
418 // 0x00000002 [1] CLK_ADC_ADC0 (0)
419 // 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0)
420 io_ro_32 enabled0;
421
422 _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
423 // indicates the state of the clock enable
424 // 0x00004000 [14] CLK_SYS_XOSC (0)
425 // 0x00002000 [13] CLK_SYS_XIP (0)
426 // 0x00001000 [12] CLK_SYS_WATCHDOG (0)
427 // 0x00000800 [11] CLK_USB_USBCTRL (0)
428 // 0x00000400 [10] CLK_SYS_USBCTRL (0)
429 // 0x00000200 [9] CLK_SYS_UART1 (0)
430 // 0x00000100 [8] CLK_PERI_UART1 (0)
431 // 0x00000080 [7] CLK_SYS_UART0 (0)
432 // 0x00000040 [6] CLK_PERI_UART0 (0)
433 // 0x00000020 [5] CLK_SYS_TIMER (0)
434 // 0x00000010 [4] CLK_SYS_TBMAN (0)
435 // 0x00000008 [3] CLK_SYS_SYSINFO (0)
436 // 0x00000004 [2] CLK_SYS_SYSCFG (0)
437 // 0x00000002 [1] CLK_SYS_SRAM5 (0)
438 // 0x00000001 [0] CLK_SYS_SRAM4 (0)
439 io_ro_32 enabled1;
440 };
441 // (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes)
442 _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
443 // indicates the state of the clock enable
444 // 0x80000000 [31] CLK_SYS_SRAM3 (0)
445 // 0x40000000 [30] CLK_SYS_SRAM2 (0)
446 // 0x20000000 [29] CLK_SYS_SRAM1 (0)
447 // 0x10000000 [28] CLK_SYS_SRAM0 (0)
448 // 0x08000000 [27] CLK_SYS_SPI1 (0)
449 // 0x04000000 [26] CLK_PERI_SPI1 (0)
450 // 0x02000000 [25] CLK_SYS_SPI0 (0)
451 // 0x01000000 [24] CLK_PERI_SPI0 (0)
452 // 0x00800000 [23] CLK_SYS_SIO (0)
453 // 0x00400000 [22] CLK_SYS_RTC (0)
454 // 0x00200000 [21] CLK_RTC_RTC (0)
455 // 0x00100000 [20] CLK_SYS_ROSC (0)
456 // 0x00080000 [19] CLK_SYS_ROM (0)
457 // 0x00040000 [18] CLK_SYS_RESETS (0)
458 // 0x00020000 [17] CLK_SYS_PWM (0)
459 // 0x00010000 [16] CLK_SYS_PSM (0)
460 // 0x00008000 [15] CLK_SYS_PLL_USB (0)
461 // 0x00004000 [14] CLK_SYS_PLL_SYS (0)
462 // 0x00002000 [13] CLK_SYS_PIO1 (0)
463 // 0x00001000 [12] CLK_SYS_PIO0 (0)
464 // 0x00000800 [11] CLK_SYS_PADS (0)
465 // 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0)
466 // 0x00000200 [9] CLK_SYS_JTAG (0)
467 // 0x00000100 [8] CLK_SYS_IO (0)
468 // 0x00000080 [7] CLK_SYS_I2C1 (0)
469 // 0x00000040 [6] CLK_SYS_I2C0 (0)
470 // 0x00000020 [5] CLK_SYS_DMA (0)
471 // 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
472 // 0x00000008 [3] CLK_SYS_BUSCTRL (0)
473 // 0x00000004 [2] CLK_SYS_ADC (0)
474 // 0x00000002 [1] CLK_ADC_ADC (0)
475 // 0x00000001 [0] CLK_SYS_CLOCKS (0)
476 io_ro_32 enabled[2];
477 };
478
479 _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
480 // Raw Interrupts
481 // 0x00000001 [0] CLK_SYS_RESUS (0)
482 io_ro_32 intr;
483
484 _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
485 // Interrupt Enable
486 // 0x00000001 [0] CLK_SYS_RESUS (0)
487 io_rw_32 inte;
488
489 _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
490 // Interrupt Force
491 // 0x00000001 [0] CLK_SYS_RESUS (0)
492 io_rw_32 intf;
493
494 _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
495 // Interrupt status after masking & forcing
496 // 0x00000001 [0] CLK_SYS_RESUS (0)
497 io_ro_32 ints;
499
500#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
501static_assert(sizeof (clocks_hw_t) == 0x00c8, "");
502
503#endif // _HARDWARE_STRUCTS_CLOCKS_H
504
clock_dest_num_rp2040
Clock destination numbers on RP2040 (used as typedef clock_dest_num_t)
Definition clocks.h:48
enum clock_dest_num_rp2040 clock_dest_num_t
Clock destination numbers on RP2040 (used as typedef clock_dest_num_t)
clock_num_rp2040
Clock numbers on RP2040 (used as typedef clock_num_t)
Definition clocks.h:30
enum clock_num_rp2040 clock_num_t
Clock numbers on RP2040 (used as typedef clock_num_t)
@ CLK_DEST_SYS_BUSCTRL
Select SYS_BUSCTRL as clock destination.
Definition clocks.h:52
@ CLK_DEST_SYS_PIO1
Select SYS_PIO1 as clock destination.
Definition clocks.h:62
@ CLK_DEST_SYS_SIO
Select SYS_SIO as clock destination.
Definition clocks.h:72
@ CLK_DEST_SYS_PSM
Select SYS_PSM as clock destination.
Definition clocks.h:65
@ CLK_DEST_SYS_UART0
Select SYS_UART0 as clock destination.
Definition clocks.h:88
@ CLK_DEST_SYS_TBMAN
Select SYS_TBMAN as clock destination.
Definition clocks.h:85
@ CLK_DEST_SYS_PLL_USB
Select SYS_PLL_USB as clock destination.
Definition clocks.h:64
@ CLK_DEST_SYS_USBCTRL
Select SYS_USBCTRL as clock destination.
Definition clocks.h:91
@ CLK_DEST_PERI_UART0
Select PERI_UART0 as clock destination.
Definition clocks.h:87
@ CLK_DEST_SYS_I2C1
Select SYS_I2C1 as clock destination.
Definition clocks.h:56
@ CLK_DEST_SYS_PADS
Select SYS_PADS as clock destination.
Definition clocks.h:60
@ CLK_DEST_SYS_XIP
Select SYS_XIP as clock destination.
Definition clocks.h:94
@ CLK_DEST_SYS_SRAM1
Select SYS_SRAM1 as clock destination.
Definition clocks.h:78
@ CLK_DEST_SYS_SRAM4
Select SYS_SRAM4 as clock destination.
Definition clocks.h:81
@ CLK_DEST_PERI_UART1
Select PERI_UART1 as clock destination.
Definition clocks.h:89
@ CLK_DEST_SYS_WATCHDOG
Select SYS_WATCHDOG as clock destination.
Definition clocks.h:93
@ CLK_DEST_SYS_ROSC
Select SYS_ROSC as clock destination.
Definition clocks.h:69
@ CLK_DEST_SYS_PIO0
Select SYS_PIO0 as clock destination.
Definition clocks.h:61
@ CLK_DEST_SYS_SRAM2
Select SYS_SRAM2 as clock destination.
Definition clocks.h:79
@ CLK_DEST_SYS_SRAM5
Select SYS_SRAM5 as clock destination.
Definition clocks.h:82
@ CLK_DEST_SYS_SPI1
Select SYS_SPI1 as clock destination.
Definition clocks.h:76
@ CLK_DEST_ADC_ADC
Select ADC_ADC as clock destination.
Definition clocks.h:50
@ CLK_DEST_RTC_RTC
Select RTC_RTC as clock destination.
Definition clocks.h:70
@ CLK_DEST_SYS_JTAG
Select SYS_JTAG as clock destination.
Definition clocks.h:58
@ CLK_DEST_SYS_IO
Select SYS_IO as clock destination.
Definition clocks.h:57
@ CLK_DEST_SYS_SYSINFO
Select SYS_SYSINFO as clock destination.
Definition clocks.h:84
@ CLK_DEST_PERI_SPI0
Select PERI_SPI0 as clock destination.
Definition clocks.h:73
@ CLK_DEST_SYS_VREG_AND_CHIP_RESET
Select SYS_VREG_AND_CHIP_RESET as clock destination.
Definition clocks.h:59
@ CLK_DEST_SYS_SYSCFG
Select SYS_SYSCFG as clock destination.
Definition clocks.h:83
@ CLK_DEST_SYS_PWM
Select SYS_PWM as clock destination.
Definition clocks.h:66
@ CLK_DEST_SYS_TIMER
Select SYS_TIMER as clock destination.
Definition clocks.h:86
@ CLK_DEST_SYS_SRAM0
Select SYS_SRAM0 as clock destination.
Definition clocks.h:77
@ CLK_DEST_SYS_CLOCKS
Select SYS_CLOCKS as clock destination.
Definition clocks.h:49
@ CLK_DEST_SYS_UART1
Select SYS_UART1 as clock destination.
Definition clocks.h:90
@ CLK_DEST_SYS_SPI0
Select SYS_SPI0 as clock destination.
Definition clocks.h:74
@ CLK_DEST_SYS_PLL_SYS
Select SYS_PLL_SYS as clock destination.
Definition clocks.h:63
@ CLK_DEST_SYS_BUSFABRIC
Select SYS_BUSFABRIC as clock destination.
Definition clocks.h:53
@ CLK_DEST_SYS_DMA
Select SYS_DMA as clock destination.
Definition clocks.h:54
@ CLK_DEST_PERI_SPI1
Select PERI_SPI1 as clock destination.
Definition clocks.h:75
@ CLK_DEST_USB_USBCTRL
Select USB_USBCTRL as clock destination.
Definition clocks.h:92
@ CLK_DEST_SYS_I2C0
Select SYS_I2C0 as clock destination.
Definition clocks.h:55
@ CLK_DEST_SYS_RESETS
Select SYS_RESETS as clock destination.
Definition clocks.h:67
@ CLK_DEST_SYS_SRAM3
Select SYS_SRAM3 as clock destination.
Definition clocks.h:80
@ CLK_DEST_SYS_ADC
Select SYS_ADC as clock destination.
Definition clocks.h:51
@ CLK_DEST_SYS_ROM
Select SYS_ROM as clock destination.
Definition clocks.h:68
@ CLK_DEST_SYS_RTC
Select SYS_RTC as clock destination.
Definition clocks.h:71
@ CLK_DEST_SYS_XOSC
Select SYS_XOSC as clock destination.
Definition clocks.h:95
@ clk_rtc
Select CLK_RTC as clock source.
Definition clocks.h:40
@ clk_gpout0
Select CLK_GPOUT0 as clock source.
Definition clocks.h:31
@ clk_gpout2
Select CLK_GPOUT2 as clock source.
Definition clocks.h:33
@ clk_peri
Select CLK_PERI as clock source.
Definition clocks.h:37
@ clk_gpout1
Select CLK_GPOUT1 as clock source.
Definition clocks.h:32
@ clk_ref
Select CLK_REF as clock source.
Definition clocks.h:35
@ clk_sys
Select CLK_SYS as clock source.
Definition clocks.h:36
@ clk_usb
Select CLK_USB as clock source.
Definition clocks.h:38
@ clk_gpout3
Select CLK_GPOUT3 as clock source.
Definition clocks.h:34
@ clk_adc
Select CLK_ADC as clock source.
Definition clocks.h:39
Definition clocks.h:100
Definition clocks.h:124
Definition clocks.h:187
Definition clocks.h:137