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v2.0.0 (RP2040)
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watchdog.h
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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#ifndef _HARDWARE_STRUCTS_WATCHDOG_H
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#define _HARDWARE_STRUCTS_WATCHDOG_H
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#include "
hardware/address_mapped.h
"
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#include "hardware/regs/watchdog.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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typedef
struct
{
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_REG_(WATCHDOG_CTRL_OFFSET)
// WATCHDOG_CTRL
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// Watchdog control
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// 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset
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// 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused
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// 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode
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// 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode
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// 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric
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// 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)...
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io_rw_32 ctrl;
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_REG_(WATCHDOG_LOAD_OFFSET)
// WATCHDOG_LOAD
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// Load the watchdog timer.
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// 0x00ffffff [23:0] LOAD (0x000000)
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io_wo_32 load;
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_REG_(WATCHDOG_REASON_OFFSET)
// WATCHDOG_REASON
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// Logs the reason for the last reset.
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// 0x00000002 [1] FORCE (0)
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// 0x00000001 [0] TIMER (0)
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io_ro_32 reason;
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// (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
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_REG_(WATCHDOG_SCRATCH0_OFFSET)
// WATCHDOG_SCRATCH0
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// Scratch register
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// 0xffffffff [31:0] SCRATCH0 (0x00000000)
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io_rw_32 scratch[8];
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_REG_(WATCHDOG_TICK_OFFSET)
// WATCHDOG_TICK
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// Controls the tick generator
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// 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles...
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// 0x00000400 [10] RUNNING (-) Is the tick generator running?
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// 0x00000200 [9] ENABLE (1) start / stop tick generation
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// 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick
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io_rw_32 tick;
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}
watchdog_hw_t
;
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#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE)
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static_assert
(
sizeof
(
watchdog_hw_t
) == 0x0030,
""
);
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#endif
// _HARDWARE_STRUCTS_WATCHDOG_H
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address_mapped.h
watchdog_hw_t
Definition
watchdog.h:26