DPDK 24.11.0-rc2
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rte_eth_ctrl.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
3 */
4
5#ifndef _RTE_ETH_CTRL_H_
6#define _RTE_ETH_CTRL_H_
7
8#include <stdint.h>
9#include <rte_common.h>
10#include <rte_ether.h>
11#include "rte_flow.h"
12#include "rte_ethdev.h"
13
26#define RTE_NTUPLE_FLAGS_DST_IP 0x0001
27#define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
28#define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
29#define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
30#define RTE_NTUPLE_FLAGS_PROTO 0x0010
31#define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
33#define RTE_5TUPLE_FLAGS ( \
34 RTE_NTUPLE_FLAGS_DST_IP | \
35 RTE_NTUPLE_FLAGS_SRC_IP | \
36 RTE_NTUPLE_FLAGS_DST_PORT | \
37 RTE_NTUPLE_FLAGS_SRC_PORT | \
38 RTE_NTUPLE_FLAGS_PROTO)
39
40#define RTE_2TUPLE_FLAGS ( \
41 RTE_NTUPLE_FLAGS_DST_PORT | \
42 RTE_NTUPLE_FLAGS_PROTO)
43
44#define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F
51 uint16_t flags;
52 uint32_t dst_ip;
53 uint32_t dst_ip_mask;
54 uint32_t src_ip;
55 uint32_t src_ip_mask;
56 uint16_t dst_port;
57 uint16_t dst_port_mask;
58 uint16_t src_port;
59 uint16_t src_port_mask;
60 uint8_t proto;
61 uint8_t proto_mask;
65 uint8_t tcp_flags;
66 uint16_t priority;
68 uint16_t queue;
69};
70
71#define RTE_ETH_FDIR_MAX_FLEXLEN 16
72#define RTE_ETH_INSET_SIZE_MAX 128
78 RTE_ETH_INPUT_SET_UNKNOWN = 0,
79
80 /* L2 */
81 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
82 RTE_ETH_INPUT_SET_L2_DST_MAC,
83 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
84 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
85 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
86
87 /* L3 */
88 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
89 RTE_ETH_INPUT_SET_L3_DST_IP4,
90 RTE_ETH_INPUT_SET_L3_SRC_IP6,
91 RTE_ETH_INPUT_SET_L3_DST_IP6,
92 RTE_ETH_INPUT_SET_L3_IP4_TOS,
93 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
94 RTE_ETH_INPUT_SET_L3_IP6_TC,
95 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
96 RTE_ETH_INPUT_SET_L3_IP4_TTL,
97 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
98
99 /* L4 */
100 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
101 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
102 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
103 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
104 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
105 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
106 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
107
108 /* Tunnel */
109 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
110 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
111 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
112 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
113 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
114
115 /* Flexible Payload */
116 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
117 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
118 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
119 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
120 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
121 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
122 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
123 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
124
125 RTE_ETH_INPUT_SET_DEFAULT = 65533,
126 RTE_ETH_INPUT_SET_NONE = 65534,
127 RTE_ETH_INPUT_SET_MAX = 65535,
128};
129
134 RTE_ETH_INPUT_SET_OP_UNKNOWN,
137 RTE_ETH_INPUT_SET_OP_MAX
138};
139
140
146 uint16_t flow_type;
147 uint16_t inset_size;
150};
151
156 uint16_t ether_type;
157};
158
163 uint32_t src_ip;
164 uint32_t dst_ip;
165 uint8_t tos;
166 uint8_t ttl;
167 uint8_t proto;
168};
169
175 uint16_t src_port;
176 uint16_t dst_port;
177};
178
184 uint16_t src_port;
185 uint16_t dst_port;
186};
187
193 uint16_t src_port;
194 uint16_t dst_port;
195 uint32_t verify_tag;
196};
197
202 uint32_t src_ip[4];
203 uint32_t dst_ip[4];
204 uint8_t tc;
205 uint8_t proto;
206 uint8_t hop_limits;
207};
208
214 uint16_t src_port;
215 uint16_t dst_port;
216};
217
223 uint16_t src_port;
224 uint16_t dst_port;
225};
226
232 uint16_t src_port;
233 uint16_t dst_port;
234 uint32_t verify_tag;
235};
236
241 struct rte_ether_addr mac_addr;
242};
243
248 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
249 RTE_FDIR_TUNNEL_TYPE_NVGRE,
250 RTE_FDIR_TUNNEL_TYPE_VXLAN,
251};
252
260 uint32_t tunnel_id;
261 struct rte_ether_addr mac_addr;
262};
263
269 struct rte_eth_l2_flow l2_flow;
270 struct rte_eth_udpv4_flow udp4_flow;
271 struct rte_eth_tcpv4_flow tcp4_flow;
272 struct rte_eth_sctpv4_flow sctp4_flow;
273 struct rte_eth_ipv4_flow ip4_flow;
274 struct rte_eth_udpv6_flow udp6_flow;
275 struct rte_eth_tcpv6_flow tcp6_flow;
276 struct rte_eth_sctpv6_flow sctp6_flow;
277 struct rte_eth_ipv6_flow ipv6_flow;
278 struct rte_eth_mac_vlan_flow mac_vlan_flow;
279 struct rte_eth_tunnel_flow tunnel_flow;
280};
281
286 uint16_t vlan_tci;
289 uint8_t is_vf;
290 uint16_t dst_id;
291};
292
297 uint16_t flow_type;
302};
303
308 RTE_ETH_FDIR_ACCEPT = 0,
309 RTE_ETH_FDIR_REJECT,
310 RTE_ETH_FDIR_PASSTHRU,
311};
312
323
336
346
369
374 RTE_ETH_PAYLOAD_UNKNOWN = 0,
375 RTE_ETH_RAW_PAYLOAD,
376 RTE_ETH_L2_PAYLOAD,
377 RTE_ETH_L3_PAYLOAD,
378 RTE_ETH_L4_PAYLOAD,
379 RTE_ETH_PAYLOAD_MAX = 8,
380};
381
394
400 uint16_t flow_type;
403};
404
410 uint16_t nb_payloads;
411 uint16_t nb_flexmasks;
412 struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
414 struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
416};
417
428
429#define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
430#define RTE_FLOW_MASK_ARRAY_SIZE \
431 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
432
466
472 uint32_t collision;
473 uint32_t free;
474 uint32_t maxhash;
477 uint32_t maxlen;
478 uint64_t add;
479 uint64_t remove;
480 uint64_t f_add;
481 uint64_t f_remove;
482 uint32_t guarant_cnt;
483 uint32_t best_cnt;
484};
485
486#endif /* _RTE_ETH_CTRL_H_ */
#define RTE_ETH_INSET_SIZE_MAX
rte_eth_fdir_behavior
rte_eth_fdir_tunnel_type
rte_eth_input_set_field
rte_eth_fdir_status
@ RTE_ETH_FDIR_NO_REPORT_STATUS
@ RTE_ETH_FDIR_REPORT_ID_FLEX_4
@ RTE_ETH_FDIR_REPORT_FLEX_8
@ RTE_ETH_FDIR_REPORT_ID
rte_fdir_mode
@ RTE_FDIR_MODE_NONE
@ RTE_FDIR_MODE_PERFECT
@ RTE_FDIR_MODE_SIGNATURE
@ RTE_FDIR_MODE_PERFECT_TUNNEL
@ RTE_FDIR_MODE_PERFECT_MAC_VLAN
rte_filter_input_set_op
@ RTE_ETH_INPUT_SET_SELECT
@ RTE_ETH_INPUT_SET_ADD
rte_eth_payload_type
#define RTE_ETH_FDIR_MAX_FLEXLEN
enum rte_eth_fdir_status report_status
enum rte_eth_fdir_behavior behavior
struct rte_eth_fdir_input input
struct rte_eth_fdir_action action
struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]
struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]
uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]
uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]
uint32_t flex_payload_unit
uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
uint32_t max_flexpayload
struct rte_eth_fdir_flex_conf flex_conf
uint16_t flex_payload_limit
enum rte_fdir_mode mode
uint32_t max_flex_payload_segment_num
struct rte_eth_fdir_flow_ext flow_ext
union rte_eth_fdir_flow flow
struct rte_eth_ipv6_flow ipv6_mask
struct rte_eth_ipv4_flow ipv4_mask
enum rte_eth_payload_type type
uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN]
uint32_t dst_ip[4]
uint32_t src_ip[4]
uint16_t ether_type
struct rte_ether_addr mac_addr
struct rte_eth_ipv4_flow ip
struct rte_eth_ipv6_flow ip
struct rte_eth_ipv4_flow ip
struct rte_eth_ipv6_flow ip
struct rte_ether_addr mac_addr
enum rte_eth_fdir_tunnel_type tunnel_type
struct rte_eth_ipv4_flow ip
struct rte_eth_ipv6_flow ip